① Device selection, requirement analysis, architecture design, RTL implementation, simulation verification, static timing analysis, comprehensive layout and optimization, and on-board debugging

② Provide hardware acceleration solutions for the company's low-latency trading system

③ Joint debugging of software and hardware systems, performance optimization

④ Help to optimize the performance of the trading system

⑤ Track new technologies in the industry

⑥ Able to realize complete transaction system solutions.

① Electronics, communication, computer related majors, full-time 211 university or above bachelor degree or above

② More than five years of FPGA and C++ development experience

③ Strong VHDL or Verilog programming ability, good code and documentation style

④ Proficient in simulation environments such as Modelsim and Questasim

⑤ Familiar with the device structure of mainstream FPGAs such as Xilinx and Altera, proficient in high-speed digital logic design, timing constraints, timing and area optimization methods

⑥ There is an efficient FPGA debugging method

⑦ Experience in high-frequency trading system development, high-performance low-latency FPGA development, and PCIe interface development is preferred

⑧ In-depth understanding of linux operating system, rich experience in multi-core programming, in-depth understanding of I/O subsystem, memory management system, network protocol stack is preferred

⑨ Profound sensitivity to the principle of network card driver and performance bottleneck of the network protocol stack, the ability to modify the underlying driver, and the experience in coordination and tuning of upper-layer applications is preferred.